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DG894
Vishay Siliconix
Component Video Selector
FEATURES
D D D D D D D Wide Bandwidth: 200 MHz Very Low Crosstalk: -70 dB at 5 MHz CMOS Compatible I2C Bus Compatible Fast Switching--tON: <200 ns Low rDS(on): 44 W Single Supply Capability
BENEFITS
D D D D D Low Insertion Loss Improved System Performance Reduced Power Consumption Easily Interfaced Future System Expansion via I2C Bus
APPLICATIONS
D Component Video Switching: RGB + SYNC, S-VHS, Y-C, etc. D Audio/Video Routing D Digital TV D ATE D I2C Bus Audio/Video Systems D SCART Video Switching
DESCRIPTION
The DG894 is a monolithic video selector designed for switching a variety of component video signals. The low on-resistance and low capacitance of the DG894 make it ideal for video/audio signal routing. Switch control can be through direct CMOS addressing or through the two-wire I2C bus. The DG894 is built on the Vishay Siliconix proprietary D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic and drivers. Low-capacitance DMOS FETs are used to achieve high levels of off isolation at low cost.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Dual-In-Line and SOIC
VDD Y1 C1 GND Y2 C2 VSS ROUT GOUT BOUT FBOUT FB2 R2 G2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Control Logic/Drivers
28 27 26 25 24 23 22 21 20 19 18 17 16 15
C0 Y0 VDD COUT YOUT SMO SCL SDA SEL R1 G1 B1 FB1 B2
TRUTH TABLE
SMO
0 0 1 1 1 1 1 1 1 1
SEL
0 1 0 0 0 0 1 1 1 1
SDA
I2C
SCL
Function/Switch On
Bus Operation, Address A0 = "1"
I2C Bus Operation, Address A0 = "0" 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 All switches off Y0, C0 Y1, C1 Y2, C2 R1, G1, B1, F1 R2, G2, B2, F2 R1, G1, B1, F1, Y1, C1 R2, G2, B2, F2, Y2, C2
ORDERING INFORMATION
Temp Range
-40 to 85_C -40 to 85_C
Package
28-Pin Plastic DIP 28-Pin Wide Body SOIC
Part Number
DG894DJ DG894DW
Top View
Document Number: 70072 S-52433--Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 19 V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 19 V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3 V to (V+) +0.3 V or 20 mA, whichever occurs first Signal Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS -0.3 V to 8 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current (Any Terminal) Pulsed 1 ms, 10% Duty Cycle Max . . . . . . . . 40 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)a 28-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW 28-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Notes: a. All leads welded or soldered to PC board.
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Ranged VANALOG rDS(on) IS = -10 mA, VD = 0 V DrDS(on) IS(off) ID(off) ID(on) VS = 4 V, VD = 0 V VD = 4 V, VS = 0 V VD = VS = 4 V Room Room Full Room Full Room Full -10 -100 -10 -100 -10 -100 10 -0.05 -0.05 -0.07 10 100 10 100 10 100 nA VDD = 12 V, VSS = GND VDD = 12 V, VSS = -5 V Full Full Room Full 0 -2 44 51 4 2 100 150 V
Limits
-40 to 85_C
Symbol
VDD = 12 V, VSS = -5 V VINH = 3 V, VINL = 1.5 Ve
Tempa
Minc
Typb
Maxc
Unit
Drain-Source On-Resistance Resistance Match Between Channels Source Off Leakage Current Drain Off Leakage Current Total Switch On Leakage Current
W
Input
Input Voltage High Input Voltage Low Input Threshold Temp Coefficient of Input Threshold Input Current Output Voltage Low VINH VINL Vth TCth IIN VOL VIN = GND or VDD Pin 21, During Acknowledge, IOL = 3 mA Full Full Room Full Room Full Room -1 -20 3 2.55 2.55 2.55 -200 0.05 1 20 0.4 mV/ _C mA V 1.5 V
Dynamic
Input Capacitanced On State Input Capacitanced Off State Input Capacitanced Off State Output Capacitanced Bandwidthd Turn On Time Turn Off Time SCL Max Clock Frequency Component Crosstalk Channel Crosstalk www.siliconix.com S FaxBack 408-970-5600 Cin CS(on) CS(off) CD(off) BW tON tOFF FSCL(MAX) XTALK(CO) XTALK(CH) RIN = 10 W, RL = 1 kW , f = 5 MHz, See Figure 2 and 3 MH S Fi d Pin 21, 22 VS = VD = 0 V VS = 0 V VD = 0 V RL = 50 W, See Figure 1 RL = 1 kW, CL = 35 pF, 50% to 90% VSS = -5 V, 0 V, VS = 3 V, See Figure 1 Room Room Room Room Room Room Room Full Room Room 100 -85 dB -85 Document Number: 70072 S-52433--Rev. D, 06-Sep-99 200 3 10 4 4 500 200 ns 180 kHz 10 15 pF F 8 8 MHz
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DG894
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specified Parameter Supply Voltage
Positive Supply Current Negative Supply Current I+ All Control Inputs 0 V, 5 V I- Room Full Room Full -8 -10 3 4 -2.5 -3.0 8 10
Limits
-40 to 85_C
Symbol
VDD = 12 V, VSS = -5 V VINH = 3 V, VINL = 1.5 Ve
Tempa
Minc
Typb
Maxc
Unit
mA
Notes: a. Room = 25_C, Full = as determined by the operating temperature suffix. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Guaranteed by design, not subject to production test. e. VIN = input voltage to perform proper function.
Purchase of Vishay Siliconix DG894 components conveys a license to use them in the I2C system as defined by Philips.
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
200 r DS(on) Drain-Source On-Resistance ( W ) - 180 160 140 120 100 85_C 80 25_C 60 40 20 -4 -2 2 4 VD - Drain Voltage (V) 0 6 8 -40_C
rDS(on) vs. Drain Voltage
V+ = 12 V V- = -5 V IS = -10 mA r DS(on) Drain-Source On-Resistance ( W ) -
200 180 160 140 120 100 80 25_C 60 40 20 0
rDS(on) vs. Drain Voltage
V+ = 12 V V- = 0 V IS = -10 mA
85_C
-40_C
2
4 VD - Drain Voltage (V)
6
8
106
tON vs. Bipolar Supply Voltage
V- = -5 V See Figure 1
45.5
tOFF vs. Bipolar Supply Voltage
85_C
100 85_C 94
43.5 V- = -5 V See Figure 1 t OFF (ns) 41.5 25_C 39.5
t ON (ns)
88 25_C 82 -40_C 76 10.8 11.2 11.6 12.0 12.4 V+ - Positive Supply (V) 12.8 13.2
37.5
-40_C
35.5 10.8 11.2 11.6 12.0 12.4 V+ - Positive Supply (V) 12.8 13.2
Document Number: 70072 S-52433--Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
tON vs. Unipolar Supply Voltage
108 V- = 0 V See Figure 1 100 54 85_C 51 V- = 0 V See Figure 1 57
tOFF vs. Unipolar Supply Voltage
85_C
t OFF (ns) 25_C
t ON (ns)
92
84
48 25_C
76 -40_C
45 -40_C
68 10.8 11.2 11.6 12.0 12.4 12.8 13.2 V+ - Positive Supply (V)
42 10.8 11.2 11.6 12.0 12.4 12.8 13.2
V+ - Positive Supply (V)
SDA Output Current vs. Supply Voltage
10 V- = -5 V 8 VOL = 0.4 V TA = 25_C Current (mA) 6 Current (mA) V- = 0 V 10 12
SDA Output Current vs. Temperature
V- = 0 V 8 6 V+= 12 V VOL = 0.4 V
V- = -5 V
4
Specification Minimum Limit
4 2
Specification Minimum Limit
2
0 10.8 11.2 11.6 12.0 VSUPPLY (V) 12.4 12.8 13.2
0 -40 -20 0 20 40 60 80 100 Temperature (_C)
Component Crosstalk
120 110 100 90 dB 80 70 60 50 40 1 2 3 4 5 10 dB VDS = +12 V VSS = -5 V RIN = 10 W RL = 1 kW See Figure 2 120 110 100 90 80 70 60 50 40 1
Channel Crosstalk
VDD = +12 V VSS = -5 V RIN = 10 W RL = 1 kW See Figure 3
2
3
4
5
10
f - Frequency (MHz)
f - Frequency (MHz)
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Document Number: 70072 S-52433--Rev. D, 06-Sep-99
DG894
Vishay Siliconix
TEST CIRCUITS
+12 V
V+ VS S IN 3V GND V- RL 1 kW CL 35 pF D VO Logic Input Switch Input
5V 50%
VS 90%
Switch Output -5 V
0V tON tOFF
CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on)
FIGURE 1. Switching Time
B1 FB1 e.g., Y or C e.g., Y1 or C1 e.g., Y2 or C2 YOUT or COUT 10 W B2 R2 G2
BOUT FBOUT
RL 1 kW
10 W
RL 1 kW
10 W
1 kW
1 kW
VOUT XTALK(CO) + 20 log 10 V IN
VOUT XTALK(CH) + 20 log10 V IN
FIGURE 2. Component Crosstalk
+12 V C V+ VS Rg = 75 W RL 50 W GND V- S D
FIGURE 3. Channel Crosstalk
VO
-5 V
FIGURE 4. Bandwidth
Document Number: 70072 S-52433--Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
OPERATING VOLTAGE RANGE
20 18 16 Operating Voltage Area 14 12 10 8 6 4 2 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 V- - Negative Supply Voltage (V) 0 -0.0 V+ - Positive Supply Voltage (V)
f a Data Sheet Test Conditions
FIGURE 5.
PIN DESCRIPTION
Symbol
Y0, Y1, Y2 C0, C1, C2 R1, R2, G1, G2, B1, B2, FB1, FB2 GND VDD VSS YOUT , COUT ROUT , GOUT , BOUT , FBOUT SMO SDA SCL SEL An analog channel input, typically luminance. An analog channel input, typically chrominance. An analog channel input, typically "red", "green", "blue" or "fast blanking", as appropriate. Analog and digital ground. Positive supply voltagea Negative supply voltage An analog channel output, typically luminance or chrominance, as appropriate An analog channel output, typically "red", "green", "blue" or "fast blanking", as appropriate. A low selects serial mode (I2C) operation. A high selects CMOS operation. Serial data lineb Serial clock lineb CMOS control line or I2C addressc select line
Description
Notes: a. Both VDD pins (Pin 1 and Pin 26) must be connected for proper operation. b. SDA and SCL pins become CMOS control inputs when SMO = High. c. The SEL pin, in I2C bus operation (i.e., with SMO low), is the least significant bit of the device address. This allows two devices to operate on the same I2C bus, yet retain independent control.
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Document Number: 70072 S-52433--Rev. D, 06-Sep-99
DG894
Vishay Siliconix
APPLICATIONS
-5 V
+12 V
VSS Y1 C1 R1 75 W G1 75 W B1 75 W SYNC1 75 W Left2 Right2 R2 75 W G2 75 W B2 75 W SYNC2 75 W B2 FB2 G1 B1 FB1 Y2 C2
VDD YOUT COUT
Left1 Right1 R1
Left Right
+5 V
75 W R2 G2 ROUT GOUT BOUT FBOUT CLC114 +5 V SMO -5 V SEL Control Logic SDA ROUT GOUT BOUT SYNCOUT
SCL
GND
Channel Select
FIGURE 6.
Document Number: 70072 S-52433--Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
I2C Bus Operation--RGB Switching Figure 6 shows an inexpensive RGB + stereo selector. The two audio channels are switched via the C, Y terminals. The CLC114 quad video buffer drives four 75-W output lines. - - - number of devices on bus total bus capacitance supply voltage (Figure 7).
Characteristics of the I@C Bus
The I@C Bus interface is ideally suited for communication between different ICs or modules. Its salient features are:
D Two wire bidirectional serial bus
Data Transfer on the I@C Bus
If the bus is not being used, both SDA and SCL lines must be left high.
-
Serial data (SDA) and serial clock (SCL) lines
Every byte put onto the SDA line should be eight bits long (MSB first), followed by an acknowledge bit, which is generated by the receiving device.
D Multi-master system (built-in arbitration for multi-master
systems)
D Devices have independent clocks D Master and slave devices can be receivers and/or
transmitters.
D Each device has a unique address. D Maximum bus clock rate of 100 kHz. D Any number of interfaces may be connected to the bus
Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always the address byte. If this is the device's own address, the device will generate an acknowledge by pulling the SDA line low during the ninth clock pulse, then accept the data in subsequent bytes until another start or stop condition is detected.
- - -
Limited only by total capacitance of 400 pF Each pin on bus limited to 10-pF capacitance Input levels: VIL max = 1.5 V (fixed supply operation) VIH min = 3 V (fixed supply operation) VIL max = 0.3 VDD (wide range supply operation) VIH min = 0.7 VDD (wide range supply operation)
The eight bit of the address byte is the read/write bit (high = read from addressed device, low = write to the addressed device) so, for the DG894, the address is only considered valid if the R/W bit is low.
Data bytes are always acknowledged during the ninth clock pulse by the addressed device. Note that during the acknowledge period the transmitting device must leave the SDA line high.
System Configuration
Rp value depends on:
Premature termination of the data transfer is allowed by generating a stop condition at any time. When this happens, the DG894 will remain in the state defined by the last complete data byte transmitted.
Rp SCL SDA Master Transmitter/ Receiver Master Transmitter
Rp
Peripheral Device
Peripheral Device
FIGURE 7.
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DG894
Vishay Siliconix
SDA
SDA
SCL STA Start Condition STO Stop Condition
SCL
FIGURE 8. START and STOP Conditions
SDA MSB acknowledgement signal from receiver byte complete, interrupt within receiver SCL 1 STA Start Condition 2 7 8 9 ACK 1 2 3-8 9 ACK STO Stop Condition acknowledgement signal from receiver clock line held low while interrupts are serviced
FIGURE 9. Data Transfer on the I2C Bus
Timing Specifications of the I@C Bus I@C bus load conditions for timing specifications are as follows:
I@C Bus Protocol The DG894 is a slave receiver type of I@C interface and has four allocated addresses, two of which are user programmable through the SEL pin. Additional addresses may be obtained by a metal mask option for users requiring more than two DG894s on the same I@C bus. Contact Vishay Siliconix marketing for further information. After the correct address has been sent, only one data byte is needed to define the switch configuration. Subsequent data put onto the bus will update the switches until a STOP condition (or another START condition) signals that the device is no longer being addressed. The switches will then remain in their last configuration as long as power is maintained to the chip.
4 kW pull-up resistors to +5 V; 200 pF capacitor to ground. All values are referred to VIH = 3 V, VIL = 1.5 V.
Parameter
SCL Clock Frequency Bus Free Before Start Start Condition Set-up Time Start Condition Hold Time SCL and SDA Low Period SCL and SDA High Period SCL and SDA Rise Time SCL and SDA Fall Time Data Set-Up Time (WRITE) Data Hold Time (WRITE)
Symbol
fscl tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT
Min
- 4.7 4.7 4 4.7 4 - - 0.25 0*
Max
100 - - - - - 1.0 0.3 - -
Unit
kHz
ms
Power on Reset A power on reset function is provided on the DG894 to turn all switches off following power up if the I@C mode is selected. In the CMOS control mode, the switches are selected according to the state of the control inputs.
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*A transmitter must internally provide at lease a hold time to bridge the undefined region (max 300 ns) of the falling edge of the SCL. Document Number: 70072 S-52433--Rev. D, 06-Sep-99
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DG894
Vishay Siliconix
SDA
tBUF tR SCL tF tHD;STA
tHD;STA STO STA
tLOW
tHIGH tHD;DAT
tSU;DAT
tSU;STA STA
tSU;STO STO
FIGURE 10.I2C Bus Timing Diagram
Minimum Bit Stream to Set Up DG894 Switches
STA 1 1 0 1 1 A1 A0 R/W ACK X X X D4 D3 D2 D1 D0 ACK STO
Address Byte
Data Byte
STA A1 A0 R/W ACK D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 STO
= START CONDITION = 0 (programmable to "1" with metal mask change) = SEL. Address bit set by use (address is inverse of SEL logic level) = READ/WRITE bit (must be "0", only WRITE mode allowed for DG894) = Acknowledge bit ("0") generated by DG894 = 0 -- R2, G2, B2, and FB2 switches off = 1 -- R2, G2, B2, and FB2 switches on = 0 -- R1, G1, B1, and FB1 switches off = 1 -- R1, G1, B1, and FB1 switches on = 0 -- Y2, C2, switches off = 1 -- Y2, C2, switches on = 0 -- Y1, C1, switches off = 1 -- Y1, C1, switches on = 0 -- Y0 and C0 switches off = 1 -- Y0 and C0 switches on = STOP CONDITION
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Document Number: 70072 S-52433--Rev. D, 06-Sep-99

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